EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Electronic Design

FPGA Prototyping Tool Aligns With ASIC Flow

This FPGA-Synthesis Tool Offers The Prototyping Capabilities Required By RF-Intensive Systems And A Migration Path To ASIC Product Design. Over a third of all high-end ASIC designers now use FPGAs for ...
Electronic Design

RTL-To-GDSII Flow Rolls For Structured ASICs

A collaboration between Magma Design Automation and ChipX has produced a unified RTL-to-GDSII structured ASIC design flow. Based on Magma's Blast Create and Blast ...
Semiconductor Engineering

The Weather Report: 2018 Study On IC/ASIC Verification Trends

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought ...
Design-Reuse

Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications

SAN JOSE, Calif. -- March 12 2007--Altera Corporation (Nasdaq: ALTR) today announced that the U.S. Department of State has certified that the company's HardCopy(R) II structured ASIC design and ...