Design-Reuse

Parameterized Interfaces and Reusable VIP (1 of 3)

SystemVerilog based verification introduces the concept of interfaces to represent communication between design blocks. In its most elemental form a SystemVerilog interface is just a named bundle of ...
Design-Reuse

OCP 2.2 MVC Accelerates Verification Productivity

In April 2009, Mentor Graphics released the 2009.1 version of its Multiview Verification Component (MVC) library which featured an upgrade to its OCP-IP MVC to make it OCP-IP 2.2 compliant. The OCP ...
EDN

How SystemVerilog aids design and synthesis

The SystemVerilog extensions to Verilog 2001 have been getting a lot of attention lately, especially the new features designed to support verification and testbench design. But SystemVerilog also ...
EDN

System Verilog configurable coverage model in an OVM setup – concept of reusability

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...